It is known that semiconductor power devices can be formed from a wide range of technologies. For example, one technology suitable for power devices is metal oxide semiconductor field effect transistors (MOSFET). Such MOSFETs can be constructed with a negative (N-channel) structure or a positive (P-channel) structure, as known to those skilled in the art. For an N-channel MOSFET device a positive control voltage will cause the MOSFET device to turn on, whereas for a P-channel MOSFET device a negative control voltage will cause the MOSFET device to turn on.
As is well known to a person skilled in the art, the source and drain of a MOSFET device are formed in a semiconductor material, such as silicon, whilst the gate is formed from a conductive material, such as polycrystalline silicon. The gate is separated from the semiconductor material by an insulating layer, for example silicon dioxide (SiO2). A MOSFET device is susceptible to damage when a ‘breakdown’ voltage is applied to the MOSFET.
It is known that two types of voltage damage can occur to a MOSFET device, namely:                (i) Electro Static Discharge (ESD); and        (ii) Electrical Over Stress (EOS).        
In the case of EOS there are three possible failure modes. First, a breakdown voltage of the gate oxide may be reached; second, a breakdown voltage of the drain to source (BVDSS) junction may be reached; and third, a maximum junction temperature may be reached due to high temperature generated by energy discharges.
In the case of ESD there are two possible failure modes. First, the breakdown voltage of the parasitic drain-body-source bipolar transistor may be reached; and second, a breakdown voltage of the gate oxide may be reached. It is known that in the case of bipolar devices, an ESD event may cause irreversible damage, for example due to a structure junction and/or a contact overheating.
A common solution used to avoid over-voltage problems is termed a ‘snapback’ structure. Here, once a maximum operating voltage is exceeded by a pre-determined amount, an ESD protection circuit is activated. In response, the ESD protection circuit reduces the voltage level applied to the application (often in the form of an application running on an integrated circuit (IC)) into an operating voltage lower than the ‘trigger’ voltage that caused the activation. The minimum voltage value that the protection device can reach after activation is termed the ‘snapback’ voltage.
In applications such as ‘Power-Over-Ethernet (POE)’, it is mandatory to avoid use of a ‘strong snapback’ ESD protection, in an attempt to increase the application's reliability. That is, if the snapback voltage falls below the maximum operating voltage, a direct current may be generated and input to the ESD protection circuit. In some instances, the direct current may destroy the ESD protection circuit. In other instances, the ESD protection circuit is not destroyed but remains triggered by the injected current from the running application applied to the protection structure (known as a latch-up phenomenon), which results in the application failure. Such protection mechanisms are typically used to prevent latch-up due to electro-magnetic discharge effects or as a result of parasitic fast transients.
Referring now to FIG. 1, a known current 110 versus voltage 105 relationship of a snapback protection structure is illustrated in graph 100. A conception window 125 is highlighted. The conception window 125 corresponds to the region, in which the protection on-state has to be included in order to guarantee a safe and efficient operation. Furthermore, as shown, the applied voltage has to be higher than the operating voltage 140, to ensure reliable operation of the device. In addition, the maximum voltage capability 150 of the circuit (for example due to oxide breakdown) should never be exceeded. Finally, in order to guarantee robustness of the device a current value 120 is defined, up to which the protection function should be guaranteed. By combining these constraints, a maximum acceptable value of the on-state resistance R-on 115 can be estimated.
When a specific application requires a narrow ESD trigger voltage to snapback voltage window 125 (for example if the supply voltage is close to the maximum voltage capabilities of the technology), the snapback voltage 145 and triggering voltage 150 are of the same order. In this case, the ESD protection should exhibit ‘soft snapback’ or ‘no-snapback’ behaviour.
ESD protection of power devices is mostly implemented using NPN transistors in a dual-polarity configuration, often in the form of an integrated circuit in an electronic device. During the electro-static discharge, a large part of the energy is dissipated through the vertical bipolar device.
Hence, the snapback voltage is determined by the vertical transistor features, which are driven by the technology. For a ‘soft snapback’ structure, the triggering voltage has to be close to the snapback voltage of the vertical bipolar. Thus, several structures need to be stacked upon each other to reach a suitably high snapback voltage VSB value 145. Such a structure is undesirable due to the resultant high dynamic resistance and the large area of silicon being required to implement the structure.
U.S. Pat. No. 6,707,110 B2 discloses a protection mechanism that uses two transistors that are active in the same device, one being a lateral device and the other being a vertical device. NPN and PNP transistors are listed with potentially high snapback voltages. For ‘soft snapback’ protection, it is well known that the PNP has higher intrinsic capabilities. However, the PNP described in U.S. Pat. No. 6,707,110 B2 would include a P-buried layer, which is hugely difficult to implement in practice and not applicable to many technologies.
U.S. Pat. No. 6,784,029 B describes a bi-directional ESD protection structure for BiCMOS technology. The structure disclosed comprises two ‘P’ implant regions separated by an ‘N’ region, which in combination defines a PNP structure. However, such a structure is unacceptable when using vertical MOSFET technology, as vertical conduction is impossible due to there being no buried layer. Furthermore, such a structure exhibits the behaviour of a thyristor, which would thereby provide a snapback voltage that is too low and causes latch-up.
Thus, a need exists for an improved semiconductor structure, particularly one that provides improved protection against parasitic effects such as electro-static discharge. Furthermore, and in particular, a need exists for a more robust soft snapback structure, for example with a triggering voltage above 40V, that provides low R-on ESD protection and has a minimum footprint.